module scsi2sd (

	output       led_ACT,
	output       led_ERR,

	// SCSI PHY pads

	input  [9:0] scsi_A_o,
	input  [9:0] scsi_B_o,
	output [9:0] scsi_A_i,
	output [9:0] scsi_B_i,

	// MCU interface pads

	inout [15:0] mcu_AD,
	input        mcu_WRn,
	input        mcu_OEn
	input        mcu_ALE,
	input        mcu_CSn,
	output       mcu_IRQn,

	// SD/SDIO interface pads

	output       sdio_CLK,
	output       sdio_CMD,
	inout [3:0]  sdio_D,
	input        sdio_CD

);
	// On-Chip Oscillator -> System Clock
	wire sys_RST, sys_CLK;

	defparam OSCH_inst.NOM_FREQ = "24.18"; 
	OSCH OSCH_inst (.OSC(sys_CLK), .SEDSTDBY(), .STDBY(1'b0)); 

	reset_gen reset_gen_inst
	(
		.clk(sys_CLK),
		.rst_in(rst),
		.rst_out(sys_rst)
	);









	// Internal SCSI nets

	wire scsi_ATN_o;
	wire scsi_BSY_o;
	wire scsi_ACK_o;
	wire scsi_RST_o;
	wire scsi_MSG_o;
	wire scsi_SEL_o;
	wire scsi_CD_o;
	wire scsi_REQ_o;
	wire scsi_IO_o;
	wire scsi_DP_o;
	wire [7:0] scsi_D_o;

	wire scsi_ATN_i;
	wire scsi_BSY_i;
	wire scsi_ACK_i;
	wire scsi_RST_i;
	wire scsi_MSG_i;
	wire scsi_SEL_i;
	wire scsi_CD_i;
	wire scsi_REQ_i;
	wire scsi_IO_i;
	wire scsi_DP_i;
	wire [7:0] scsi_D_i;

	// Direction of connector orientation and detection lock

	wire scsi_DIR;
	wire scsi_DET;
	wire [3:0] scsi_PATERN;

	assign scsi_PATTERN = { scsi_B_i[1], scsi_B_i[0], scsi_A_i[9], scsi_A_i[8] };

	always @(posedge sys_CLK)
	begin
		if (scsi_DET)
		begin
			if (scsi_PATTERN == 4'b1010)
			begin
				scsi_DET <= 1'b0;
				scsi_DIR <= 1'b1;
			end
			else if(scsi_PATTERN == 4'b0101)
			begin
				scsi_DET <= 1'b1;
				scsi_DIR <= 1'b0;
			end
		end
	end

	// Setup SCSI routing based on detected connector orientation

	assign scsi_ATN_i  = scsi_DIR ? scsi_A_i[9] : scsi_B_i[0];
	assign scsi_BSY_i  = scsi_DIR ? scsi_A_i[7] : scsi_B_i[2];
	assign scsi_ACK_i  = scsi_DIR ? scsi_A_i[6] : scsi_B_i[3];
	assign scsi_RST_i  = scsi_DIR ? scsi_A_i[5] : scsi_B_i[4];
	assign scsi_MSG_i  = scsi_DIR ? scsi_A_i[4] : scsi_B_i[5];
	assign scsi_SEL_i  = scsi_DIR ? scsi_A_i[3] : scsi_B_i[6];
	assign scsi_CD_i   = scsi_DIR ? scsi_A_i[2] : scsi_B_i[7];
	assign scsi_REQ_i  = scsi_DIR ? scsi_A_i[1] : scsi_B_i[8];
	assign scsi_IO_i   = scsi_DIR ? scsi_A_i[0] : scsi_B_i[9];
	assign scsi_DP_i   = scsi_DIR ? scsi_B_i[1] : scsi_A_i[8];
	assign scsi_D_i[7] = scsi_DIR ? scsi_B_i[2] : scsi_A_i[7];
	assign scsi_D_i[6] = scsi_DIR ? scsi_B_i[3] : scsi_A_i[6];
	assign scsi_D_i[5] = scsi_DIR ? scsi_B_i[4] : scsi_A_i[5];
	assign scsi_D_i[4] = scsi_DIR ? scsi_B_i[5] : scsi_A_i[4];
	assign scsi_D_i[3] = scsi_DIR ? scsi_B_i[6] : scsi_A_i[3];
	assign scsi_D_i[2] = scsi_DIR ? scsi_B_i[7] : scsi_A_i[2];
	assign scsi_D_i[1] = scsi_DIR ? scsi_B_i[8] : scsi_A_i[1];
	assign scsi_D_i[0] = scsi_DIR ? scsi_B_i[9] : scsi_A_i[0];

	assign scsi_A_o[0] = scsi_DIR ? scsi_IO_o   : scsi_D_o[0];
	assign scsi_A_o[1] = scsi_DIR ? scsi_REQ_o  : scsi_D_o[1];
	assign scsi_A_o[2] = scsi_DIR ? scsi_CD_o   : scsi_D_o[2];
	assign scsi_A_o[3] = scsi_DIR ? scsi_SEL_o  : scsi_D_o[3];
	assign scsi_A_o[4] = scsi_DIR ? scsi_MSG_o  : scsi_D_o[4];
	assign scsi_A_o[5] = scsi_DIR ? scsi_RST_o  : scsi_D_o[5];
	assign scsi_A_o[6] = scsi_DIR ? scsi_ACK_o  : scsi_D_o[6];
	assign scsi_A_o[7] = scsi_DIR ? scsi_BSY_o  : scsi_D_o[7];
	assign scsi_A_o[8] = scsi_DIR ? 1'b1        : scsi_DP_o;
	assign scsi_A_o[9] = scsi_DIR ? scsi_ATN_o  : 1'b1;
	assign scsi_B_o[0] = scsi_DIR ? 1'b1        : scsi_ATN_o;
	assign scsi_B_o[1] = scsi_DIR ? scsi_DP_o   : 1'b1;
	assign scsi_B_o[2] = scsi_DIR ? scsi_D_o[7] : scsi_BSY_o;
	assign scsi_B_o[3] = scsi_DIR ? scsi_D_o[6] : scsi_ACK_o;
	assign scsi_B_o[4] = scsi_DIR ? scsi_D_o[5] : scsi_RST_o;
	assign scsi_B_o[5] = scsi_DIR ? scsi_D_o[4] : scsi_MSG_o;
	assign scsi_B_o[6] = scsi_DIR ? scsi_D_o[3] : scsi_SEL_o;
	assign scsi_B_o[7] = scsi_DIR ? scsi_D_o[2] : scsi_CD_o;
	assign scsi_B_o[8] = scsi_DIR ? scsi_D_o[1] : scsi_REQ_o;
	assign scsi_B_o[9] = scsi_DIR ? scsi_D_o[0] : scsi_IO_o;





















endmodule