[Device]
Family=machxo2
PartType=LCMXO2-7000HC
PartName=LCMXO2-7000HC-4TG144C
SpeedGrade=4
Package=TQFP144
OperatingCondition=COM
Status=S

[IP]
VendorName=Lattice Semiconductor Corporation
CoreType=LPM
CoreStatus=Demo
CoreName=RAM_DP
CoreRevision=6.2
ModuleName=scratchpad_ebr
SourceFormat=Verilog HDL
ParameterFileVersion=1.0
Date=08/05/2013
Time=01:09:09

[Parameters]
Verilog=1
VHDL=0
EDIF=1
Destination=Synplicity
Expression=BusA(0 to 7)
Order=Big Endian [MSB:LSB]
IO=0
RAddress=1024
RData=32
WAddress=1024
WData=32
enByte=0
ByteSize=9
OutputEn=0
ClockEn=0
Optimization=Speed
Reset=Sync
Reset1=Sync
Init=mem
MemFile=s:/lm32/test/bin/test_data.mem
MemFormat=hex
EnECC=0
Pipeline=0
init_data=0

[FilesGenerated]
s:/lm32/test/bin/test_data.mem=mem