SCUBA, Version Diamond_2.2_Production (99)
Sun Jul 07 18:03:14 2013

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.

    Issued command   : C:\lscc\diamond\2.2_x64\ispfpga\bin\nt64\scuba.exe -w -n pll_reset -lang verilog -synth synplify -arch xo2c00 -type pll -fin 24.18 -fclkop 48.36 -fclkop_tol 0.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1 -lock -e 
    Circuit name     : pll_reset
    Module type      : pll
    Module Version   : 5.4
    Ports            : 
	Inputs       : CLKI
	Outputs      : CLKOP, LOCK
    I/O buffer       : not inserted
    EDIF output      : suppressed
    Verilog output   : pll_reset.v
    Verilog template : pll_reset_tmpl.v
    Verilog purpose  : for synthesis and simulation
    Bus notation     : big endian
    Report output    : pll_reset.srp
    Element Usage    :
        EHXPLLJ : 1
    Estimated Resource Usage: