SCUBA, Version Diamond_2.2_Production (99)
Wed Aug 07 01:58:36 2013
  
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
  
BEGIN SCUBA Module Synthesis
  
    Issued command   : C:\lscc\diamond\2.2_x64\ispfpga\bin\nt64\scuba.exe -w -n bootrom_ebr -lang verilog -synth synplify -bl -arch xo2c00 -type ramdps -device LCMXO2-7000HC -raddr_width 12 -rwidth 32 -waddr_width 12 -wwidth 32 -rnum_words 4096 -wnum_words 4092 -cascade -1 -memfile s:/lm32/test/bin/test_code.mem -memformat hex -e 
    Circuit name     : bootrom_ebr
    Module type      : RAM_DP
    Module Version   : 6.2
    Ports            : 
    Inputs       : WrAddress[0:11], RdAddress[0:11], Data[0:31], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn
    Outputs      : Q[0:31]
    I/O buffer       : not inserted
    Memory file      : s:/lm32/test/bin/test_code.mem
    EDIF output      : suppressed
    Verilog output   : bootrom_ebr.v
    Verilog template : bootrom_ebr_tmpl.v
    Verilog testbench: tb_bootrom_ebr_tmpl.v
    Verilog purpose  : for synthesis and simulation
    Bus notation     : little endian
    Report output    : bootrom_ebr.srp
    Estimated Resource Usage:
            EBR : 16
  
END   SCUBA Module Synthesis