/* Verilog module instantiation template generated by SCUBA Diamond_2.2_Production (99) */
/* Module Version: 3.2 */
/* Sun Jul 07 18:59:25 2013 */

/* parameterized module instance */
lm32_addsub __ (.DataA( ), .DataB( ), .Cin( ), .Add_Sub( ), .Result( ), 
    .Cout( ));