/* Verilog netlist generated by SCUBA Diamond_2.2_Production (99) */
/* Module Version: 3.2 */
/* C:\lscc\diamond\2.2_x64\ispfpga\bin\nt64\scuba.exe -w -n lm32_addsub -lang verilog -synth synplify -bus_exp 7 -bb -arch xo2c00 -type addsub -width 32 -unsigned -port ci -port co -pipeline 0 -e  */
/* Sun Jul 07 18:59:25 2013 */


`timescale 1 ns / 1 ps
module lm32_addsub (DataA, DataB, Cin, Add_Sub, Result, Cout)/* synthesis NGD_DRC_MASK=1 */;
    input wire [31:0] DataA;
    input wire [31:0] DataB;
    input wire Cin;
    input wire Add_Sub;
    output wire [31:0] Result;
    output wire Cout;

    wire scuba_vhi;
    wire ci_k;
    wire co0;
    wire co1;
    wire co2;
    wire co3;
    wire co4;
    wire co5;
    wire co6;
    wire co7;
    wire co8;
    wire co9;
    wire co10;
    wire co11;
    wire co12;
    wire co13;
    wire co14;
    wire co15;
    wire add_sub_inv;
    wire co16d;
    wire co16;
    wire scuba_vlo;

    VHI scuba_vhi_inst (.Z(scuba_vhi));

    XNOR2 XNOR2_t0 (.A(Cin), .B(Add_Sub), .Z(ci_k));

    INV INV_0 (.A(Add_Sub), .Z(add_sub_inv));

    FADSU2 addsub_0 (.A0(Cin), .A1(DataA[0]), .B0(ci_k), .B1(DataB[0]), 
        .BCI(scuba_vlo), .CON(Add_Sub), .BCO(co0), .S0(), .S1(Result[0]));

    FADSU2 addsub_1 (.A0(DataA[1]), .A1(DataA[2]), .B0(DataB[1]), .B1(DataB[2]), 
        .BCI(co0), .CON(Add_Sub), .BCO(co1), .S0(Result[1]), .S1(Result[2]));

    FADSU2 addsub_2 (.A0(DataA[3]), .A1(DataA[4]), .B0(DataB[3]), .B1(DataB[4]), 
        .BCI(co1), .CON(Add_Sub), .BCO(co2), .S0(Result[3]), .S1(Result[4]));

    FADSU2 addsub_3 (.A0(DataA[5]), .A1(DataA[6]), .B0(DataB[5]), .B1(DataB[6]), 
        .BCI(co2), .CON(Add_Sub), .BCO(co3), .S0(Result[5]), .S1(Result[6]));

    FADSU2 addsub_4 (.A0(DataA[7]), .A1(DataA[8]), .B0(DataB[7]), .B1(DataB[8]), 
        .BCI(co3), .CON(Add_Sub), .BCO(co4), .S0(Result[7]), .S1(Result[8]));

    FADSU2 addsub_5 (.A0(DataA[9]), .A1(DataA[10]), .B0(DataB[9]), .B1(DataB[10]), 
        .BCI(co4), .CON(Add_Sub), .BCO(co5), .S0(Result[9]), .S1(Result[10]));

    FADSU2 addsub_6 (.A0(DataA[11]), .A1(DataA[12]), .B0(DataB[11]), .B1(DataB[12]), 
        .BCI(co5), .CON(Add_Sub), .BCO(co6), .S0(Result[11]), .S1(Result[12]));

    FADSU2 addsub_7 (.A0(DataA[13]), .A1(DataA[14]), .B0(DataB[13]), .B1(DataB[14]), 
        .BCI(co6), .CON(Add_Sub), .BCO(co7), .S0(Result[13]), .S1(Result[14]));

    FADSU2 addsub_8 (.A0(DataA[15]), .A1(DataA[16]), .B0(DataB[15]), .B1(DataB[16]), 
        .BCI(co7), .CON(Add_Sub), .BCO(co8), .S0(Result[15]), .S1(Result[16]));

    FADSU2 addsub_9 (.A0(DataA[17]), .A1(DataA[18]), .B0(DataB[17]), .B1(DataB[18]), 
        .BCI(co8), .CON(Add_Sub), .BCO(co9), .S0(Result[17]), .S1(Result[18]));

    FADSU2 addsub_10 (.A0(DataA[19]), .A1(DataA[20]), .B0(DataB[19]), .B1(DataB[20]), 
        .BCI(co9), .CON(Add_Sub), .BCO(co10), .S0(Result[19]), .S1(Result[20]));

    FADSU2 addsub_11 (.A0(DataA[21]), .A1(DataA[22]), .B0(DataB[21]), .B1(DataB[22]), 
        .BCI(co10), .CON(Add_Sub), .BCO(co11), .S0(Result[21]), .S1(Result[22]));

    FADSU2 addsub_12 (.A0(DataA[23]), .A1(DataA[24]), .B0(DataB[23]), .B1(DataB[24]), 
        .BCI(co11), .CON(Add_Sub), .BCO(co12), .S0(Result[23]), .S1(Result[24]));

    FADSU2 addsub_13 (.A0(DataA[25]), .A1(DataA[26]), .B0(DataB[25]), .B1(DataB[26]), 
        .BCI(co12), .CON(Add_Sub), .BCO(co13), .S0(Result[25]), .S1(Result[26]));

    FADSU2 addsub_14 (.A0(DataA[27]), .A1(DataA[28]), .B0(DataB[27]), .B1(DataB[28]), 
        .BCI(co13), .CON(Add_Sub), .BCO(co14), .S0(Result[27]), .S1(Result[28]));

    FADSU2 addsub_15 (.A0(DataA[29]), .A1(DataA[30]), .B0(DataB[29]), .B1(DataB[30]), 
        .BCI(co14), .CON(Add_Sub), .BCO(co15), .S0(Result[29]), .S1(Result[30]));

    FADSU2 addsub_16 (.A0(DataA[31]), .A1(scuba_vlo), .B0(DataB[31]), .B1(add_sub_inv), 
        .BCI(co15), .CON(Add_Sub), .BCO(co16), .S0(Result[31]), .S1(Cout));

    VLO scuba_vlo_inst (.Z(scuba_vlo));

    FADD2B addsubd (.A0(scuba_vlo), .A1(scuba_vlo), .B0(scuba_vlo), .B1(scuba_vlo), 
        .CI(co16), .COUT(), .S0(co16d), .S1());



    // exemplar begin
    // exemplar end

endmodule