SCUBA, Version Diamond_2.2_Production (99)
Sun Jul 07 18:59:25 2013

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.

    Issued command   : C:\lscc\diamond\2.2_x64\ispfpga\bin\nt64\scuba.exe -w -n lm32_addsub -lang verilog -synth synplify -bus_exp 7 -bb -arch xo2c00 -type mgaddsub -add_sub -width 32 -unsigned -cin -cout -pipeline 0 -e 
    Circuit name     : lm32_addsub
    Module type      : addsub
    Module Version   : 3.2
    Width            : 32
    Ports            : 
	Inputs       : DataA[31:0], DataB[31:0], Cin, Add_Sub
	Outputs      : Result[31:0], Cout
    I/O buffer       : not inserted
    Representation   : unsigned number
    EDIF output      : suppressed
    Verilog output   : lm32_addsub.v
    Verilog template : lm32_addsub_tmpl.v
    Verilog testbench: tb_lm32_addsub_tmpl.v
    Verilog purpose  : for synthesis and simulation
    Bus notation     : big endian
    Report output    : lm32_addsub.srp
    Element Usage    :
         FADD2B : 1
         FADSU2 : 17
            INV : 1
          XNOR2 : 1
    Estimated Resource Usage:
            LUT : 37