SCUBA, Version Diamond (64-bit) 3.7.1.502
Sun Mar 26 21:09:28 2017

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation,  All rights reserved.

    Issued command   : C:\lscc\diamond\3.7_x64\ispfpga\bin\nt64\scuba.exe -w -n datafifo -lang verilog -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ebfifo -depth 1024 -width 16 -rwidth 16 -no_enable -pe 256 -pf 768 
    Circuit name     : datafifo
    Module type      : ebfifo
    Module Version   : 5.8
    Ports            : 
	Inputs       : Data[15:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
	Outputs      : Q[15:0], Empty, Full, AlmostEmpty, AlmostFull
    I/O buffer       : not inserted
    EDIF output      : datafifo.edn
    Verilog output   : datafifo.v
    Verilog template : datafifo_tmpl.v
    Verilog testbench: tb_datafifo_tmpl.v
    Verilog purpose  : for synthesis and simulation
    Bus notation     : big endian
    Report output    : datafifo.srp
    Element Usage    :
        FIFO8KB : 2
    Estimated Resource Usage:
            EBR : 2