Name jride_rtcpost; Assembly 0003; Revision P2 1.0; PartNo U6 ATF1504AS; Device f1504ispplcc44; Company Retrotronics.org; Designer Alan H.; Location None; Date October 2011; property ATMEL { xor_synthesis=on }; /* property ATMEL { logic_doubling=on }; */ property ATMEL { jtag=on }; PROPERTY ATMEL { preassign keep }; PROPERTY ATMEL { TMS_pullup=on }; PROPERTY ATMEL { TDI_pullup=on }; /* * Pin assignments * * Must run this manually since the Atmel output slewrate * property doesn't work * * fit1504 jride_rtcpost.tt2 -CUPL -dev P1504C44 -JTAG ON -str output_fast RTC_WE,RTC_CS,RTC_OE * * If you wish to setup the LED drive for common cathod instead, * reverse all the output polarities * * Any speed grade CPLD may be used. */ PROPERTY ATMEL {output_fast RTC_OE,RTC_WE,RTC_CS}; Pin 43 = BCLK; Pin 1 = RESET; Pin 26 = !IDE_RESET; Pin 34 = A; Pin 31 = B; Pin 37 = C; Pin 40 = D; Pin 33 = E; Pin 39 = F; Pin 29 = G; Pin 36 = DP; Pin 28 = C1; Pin 27 = C2; Pin 14 = D0; Pin 16 = D1; Pin 17 = D2; Pin 4 = D3; Pin 6 = D4; Pin 5 = D5; Pin 8 = D6; Pin 9 = D7; Pin 11 = A0; Pin 12 = A1; Pin 19 = A6; Pin 18 = CE; Pin 2 = !IOW; Pin 44 = !IOR; Pin 20 = RTC_ALE; Pin 21 = !RTC_CS; Pin 24 = !RTC_WE; Pin 25 = !RTC_OE; /* * CE is produced on the main PLD from a full 16 address line * decode for address values 0x10-13 & 0x70-73. We further * qualify that here to produce individual decode strobes for * each function in this module. Each must be further qualified * against IOR and IOW below. */ POST_DATA_DEC = CE & !A6 & !A1 & !A0; /* 0x10 */ RTC_ADDR_DEC = CE & A6 & !A1 & !A0; /* 0x70 */ RTC_DATA_DEC = CE & A6 & !A1 & A0; /* 0x71 */ CTRL_PORT_DEC = CE & A6 & A1 & !A0; /* 0x72 */ RTC_COMBINED = CE & A6 & !A1; /* 0x70-1 */ /* * Secondary CPLD (U6) for the JR-IDE sidecar board * * This device performs address sub-decoding for the real-time * clock chip and the POST display, latching and 7-segment * decoding of the POST code register, driving of the POST LEDs, * and supplementary clocking for the RTC control strobes. In * addition the decimal point LEDs show system bus activity by * using an address lines run through a clock divider. One * decimal LED is the complement of the other for an dorky * ping-pong effect. All LEDs can be masked off. * * The PLD register map follows: * * I/O 0x10 : Dual 4-bit hex decoder to 7-segment LED displays * I/O 0x70 : Maxim DS12C887 RTC register address latch * I/O 0x71 : Maxim DS12C887 RTC register read/write data * I/O 0x72 bit 0 : Left POST digit enable = 0 / disable = 1 * bit 1 : Right POST digit enable = 0 / disable = 1 * bit 2 : Decimal point bus activity enable = 0 / disable = 1 * bit 3 : Independent IDE reset 1 = reset asserted (low) * 0 = reset inactive (high) * bit 4-7 : Reserved */ Pinnode = [reg3..0]; reg3.t = CTRL_PORT_DEC & IOW & (reg3 $ D3); reg2.t = CTRL_PORT_DEC & IOW & (reg2 $ D2); reg1.t = CTRL_PORT_DEC & IOW & (reg1 $ D1); reg0.t = CTRL_PORT_DEC & IOW & (reg0 $ D0); [reg3..0].ce = 'b'1; [reg3..0].ar = RESET; [reg3..0].ckmux = BCLK; LEFT_DE = !reg0; RIGHT_DE = !reg1; DP_EN = !reg2; IDE_RESET = RESET # reg3; /* * LED combinatorial logic / decoder * * Ensure CLK is at 50% duty by doubling it then * cut the LED switch rate down some with spare cells. * * The LED segments are organized in a 8x2 annode x cathode * matrix with the PLD sourcing and sinking all drive current * directly. Thus once console access is established, a * drive or utility should turn the LED drives off to conserve * heat, power, and life expectancy. */ Pinnode = [CD7..0]; CD0.t = 'b'1; /* 2.328 MHz */ CD1.t = CD0; /* 1.193 MHz */ CD2.t = CD0 & CD1; /* 596.6 KHz */ CD3.t = CD0 & CD1 & CD2; /* 298.3 KHz */ CD4.t = CD0 & CD1 & CD2 & CD3; /* 149.2 KHz */ CD5.t = CD0 & CD1 & CD2 & CD3 & CD4; /* 74.57 KHz */ CD6.t = CD0 & CD1 & CD2 & CD3 & CD4 & CD5; /* 37.29 KHz */ CD7.t = CD0 & CD1 & CD2 & CD3 & CD4 & CD5 & CD6; /* 18.64 KHz */ [CD7..0].ckmux = BCLK; LCLK = CD7; C1 = LCLK; C2 = !LCLK; /* Post code decimal point latch */ Pinnode = [Q7..0]; Q7.t = POST_DATA_DEC & IOW & (Q7 $ D7); Q6.t = POST_DATA_DEC & IOW & (Q6 $ D6); Q5.t = POST_DATA_DEC & IOW & (Q5 $ D5); Q4.t = POST_DATA_DEC & IOW & (Q4 $ D4); Q3.t = POST_DATA_DEC & IOW & (Q3 $ D3); Q2.t = POST_DATA_DEC & IOW & (Q2 $ D2); Q1.t = POST_DATA_DEC & IOW & (Q1 $ D1); Q0.t = POST_DATA_DEC & IOW & (Q0 $ D0); [Q7..0].ce = 'b'1; [Q7..0].ar = RESET; [Q7..0].ckmux = BCLK; FIELD HIGH = [Q7..4]; FIELD LOW = [Q3..0]; /* Segment A - Top Center */ TABLE HIGH => AH { 'b'00000000 => 'b'1; 'b'10000000 => 'b'1; 'b'00010000 => 'b'0; 'b'10010000 => 'b'1; 'b'00100000 => 'b'1; 'b'10100000 => 'b'1; 'b'00110000 => 'b'1; 'b'10110000 => 'b'0; 'b'01000000 => 'b'0; 'b'11000000 => 'b'1; 'b'01010000 => 'b'1; 'b'11010000 => 'b'0; 'b'01100000 => 'b'1; 'b'11100000 => 'b'1; 'b'01110000 => 'b'1; 'b'11110000 => 'b'1; } TABLE LOW => AL { 'b'0000 => 'b'1; 'b'1000 => 'b'1; 'b'0001 => 'b'0; 'b'1001 => 'b'1; 'b'0010 => 'b'1; 'b'1010 => 'b'1; 'b'0011 => 'b'1; 'b'1011 => 'b'0; 'b'0100 => 'b'0; 'b'1100 => 'b'1; 'b'0101 => 'b'1; 'b'1101 => 'b'0; 'b'0110 => 'b'1; 'b'1110 => 'b'1; 'b'0111 => 'b'1; 'b'1111 => 'b'1; } A = (!LCLK & AH & LEFT_DE) # (LCLK & AL & RIGHT_DE); /* Segment B - Top Right */ TABLE HIGH => BH { 'b'00000000 => 'b'1; 'b'10000000 => 'b'1; 'b'00010000 => 'b'1; 'b'10010000 => 'b'1; 'b'00100000 => 'b'1; 'b'10100000 => 'b'1; 'b'00110000 => 'b'1; 'b'10110000 => 'b'0; 'b'01000000 => 'b'1; 'b'11000000 => 'b'0; 'b'01010000 => 'b'0; 'b'11010000 => 'b'1; 'b'01100000 => 'b'0; 'b'11100000 => 'b'0; 'b'01110000 => 'b'1; 'b'11110000 => 'b'0; } TABLE LOW => BL { 'b'0000 => 'b'1; 'b'1000 => 'b'1; 'b'0001 => 'b'1; 'b'1001 => 'b'1; 'b'0010 => 'b'1; 'b'1010 => 'b'1; 'b'0011 => 'b'1; 'b'1011 => 'b'0; 'b'0100 => 'b'1; 'b'1100 => 'b'0; 'b'0101 => 'b'0; 'b'1101 => 'b'1; 'b'0110 => 'b'0; 'b'1110 => 'b'0; 'b'0111 => 'b'1; 'b'1111 => 'b'0; } B = (!LCLK & BH & LEFT_DE) # (LCLK & BL & RIGHT_DE); /* Segment C - Bottom Right*/ TABLE HIGH => CH { 'b'00000000 => 'b'1; 'b'10000000 => 'b'1; 'b'00010000 => 'b'1; 'b'10010000 => 'b'1; 'b'00100000 => 'b'0; 'b'10100000 => 'b'1; 'b'00110000 => 'b'1; 'b'10110000 => 'b'1; 'b'01000000 => 'b'1; 'b'11000000 => 'b'0; 'b'01010000 => 'b'1; 'b'11010000 => 'b'1; 'b'01100000 => 'b'1; 'b'11100000 => 'b'0; 'b'01110000 => 'b'1; 'b'11110000 => 'b'0; } TABLE LOW => CL { 'b'0000 => 'b'1; 'b'1000 => 'b'1; 'b'0001 => 'b'1; 'b'1001 => 'b'1; 'b'0010 => 'b'0; 'b'1010 => 'b'1; 'b'0011 => 'b'1; 'b'1011 => 'b'1; 'b'0100 => 'b'1; 'b'1100 => 'b'0; 'b'0101 => 'b'1; 'b'1101 => 'b'1; 'b'0110 => 'b'1; 'b'1110 => 'b'0; 'b'0111 => 'b'1; 'b'1111 => 'b'0; } C = (!LCLK & CH & LEFT_DE) # (LCLK & CL & RIGHT_DE); /* Segment D - Bottom Center */ TABLE HIGH => DH { 'b'00000000 => 'b'1; 'b'10000000 => 'b'1; 'b'00010000 => 'b'0; 'b'10010000 => 'b'0; 'b'00100000 => 'b'1; 'b'10100000 => 'b'0; 'b'00110000 => 'b'1; 'b'10110000 => 'b'1; 'b'01000000 => 'b'0; 'b'11000000 => 'b'1; 'b'01010000 => 'b'1; 'b'11010000 => 'b'1; 'b'01100000 => 'b'1; 'b'11100000 => 'b'1; 'b'01110000 => 'b'0; 'b'11110000 => 'b'0; } TABLE LOW => DL { 'b'0000 => 'b'1; 'b'1000 => 'b'1; 'b'0001 => 'b'0; 'b'1001 => 'b'0; 'b'0010 => 'b'1; 'b'1010 => 'b'0; 'b'0011 => 'b'1; 'b'1011 => 'b'1; 'b'0100 => 'b'0; 'b'1100 => 'b'1; 'b'0101 => 'b'1; 'b'1101 => 'b'1; 'b'0110 => 'b'1; 'b'1110 => 'b'1; 'b'0111 => 'b'0; 'b'1111 => 'b'0; } D = (!LCLK & DH & LEFT_DE) # (LCLK & DL & RIGHT_DE); /* Segment E - Bottom Left*/ TABLE HIGH => EH { 'b'00000000 => 'b'1; 'b'10000000 => 'b'1; 'b'00010000 => 'b'0; 'b'10010000 => 'b'0; 'b'00100000 => 'b'1; 'b'10100000 => 'b'1; 'b'00110000 => 'b'0; 'b'10110000 => 'b'1; 'b'01000000 => 'b'0; 'b'11000000 => 'b'1; 'b'01010000 => 'b'0; 'b'11010000 => 'b'1; 'b'01100000 => 'b'1; 'b'11100000 => 'b'1; 'b'01110000 => 'b'0; 'b'11110000 => 'b'1; } TABLE LOW => EL { 'b'0000 => 'b'1; 'b'1000 => 'b'1; 'b'0001 => 'b'0; 'b'1001 => 'b'0; 'b'0010 => 'b'1; 'b'1010 => 'b'1; 'b'0011 => 'b'0; 'b'1011 => 'b'1; 'b'0100 => 'b'0; 'b'1100 => 'b'1; 'b'0101 => 'b'0; 'b'1101 => 'b'1; 'b'0110 => 'b'1; 'b'1110 => 'b'1; 'b'0111 => 'b'0; 'b'1111 => 'b'1; } E = (!LCLK & EH & LEFT_DE) # (LCLK & EL & RIGHT_DE); /* Segment F - Top Left*/ TABLE HIGH => FH { 'b'00000000 => 'b'1; 'b'10000000 => 'b'1; 'b'00010000 => 'b'0; 'b'10010000 => 'b'1; 'b'00100000 => 'b'0; 'b'10100000 => 'b'1; 'b'00110000 => 'b'0; 'b'10110000 => 'b'1; 'b'01000000 => 'b'1; 'b'11000000 => 'b'1; 'b'01010000 => 'b'1; 'b'11010000 => 'b'0; 'b'01100000 => 'b'1; 'b'11100000 => 'b'1; 'b'01110000 => 'b'0; 'b'11110000 => 'b'1; } TABLE LOW => FL { 'b'0000 => 'b'1; 'b'1000 => 'b'1; 'b'0001 => 'b'0; 'b'1001 => 'b'1; 'b'0010 => 'b'0; 'b'1010 => 'b'1; 'b'0011 => 'b'0; 'b'1011 => 'b'1; 'b'0100 => 'b'1; 'b'1100 => 'b'1; 'b'0101 => 'b'1; 'b'1101 => 'b'0; 'b'0110 => 'b'1; 'b'1110 => 'b'1; 'b'0111 => 'b'0; 'b'1111 => 'b'1; } F = (!LCLK & FH & LEFT_DE) # (LCLK & FL & RIGHT_DE); /* Segment G - Center */ TABLE HIGH => GH { 'b'00000000 => 'b'0; 'b'10000000 => 'b'1; 'b'00010000 => 'b'0; 'b'10010000 => 'b'1; 'b'00100000 => 'b'1; 'b'10100000 => 'b'1; 'b'00110000 => 'b'1; 'b'10110000 => 'b'1; 'b'01000000 => 'b'1; 'b'11000000 => 'b'0; 'b'01010000 => 'b'1; 'b'11010000 => 'b'1; 'b'01100000 => 'b'1; 'b'11100000 => 'b'1; 'b'01110000 => 'b'0; 'b'11110000 => 'b'1; } TABLE LOW => GL { 'b'0000 => 'b'0; 'b'1000 => 'b'1; 'b'0001 => 'b'0; 'b'1001 => 'b'1; 'b'0010 => 'b'1; 'b'1010 => 'b'1; 'b'0011 => 'b'1; 'b'1011 => 'b'1; 'b'0100 => 'b'1; 'b'1100 => 'b'0; 'b'0101 => 'b'1; 'b'1101 => 'b'1; 'b'0110 => 'b'1; 'b'1110 => 'b'1; 'b'0111 => 'b'0; 'b'1111 => 'b'1; } G = (!LCLK & GH & LEFT_DE) # (LCLK & GL & RIGHT_DE); /* * Divide down A6 by a set factor and display it's state * on the ping-pong'ing LED decimal points as rough indication * of system activity */ Pinnode = [ACT13..0]; ACT0.t = 'b'1; ACT1.t = ACT0; ACT2.t = ACT0 & ACT1; ACT3.t = ACT0 & ACT1 & ACT2; ACT4.t = ACT0 & ACT1 & ACT2 & ACT3; ACT5.t = ACT0 & ACT1 & ACT2 & ACT3 & ACT4; ACT6.t = ACT0 & ACT1 & ACT2 & ACT3 & ACT4 & ACT5; ACT7.t = ACT0 & ACT1 & ACT2 & ACT3 & ACT4 & ACT5 & ACT6; ACT8.t = ACT0 & ACT1 & ACT2 & ACT3 & ACT4 & ACT5 & ACT6 & ACT7; ACT9.t = ACT0 & ACT1 & ACT2 & ACT3 & ACT4 & ACT5 & ACT6 & ACT7 & ACT8; ACT10.t = ACT0 & ACT1 & ACT2 & ACT3 & ACT4 & ACT5 & ACT6 & ACT7 & ACT8 & ACT9; ACT11.t = ACT0 & ACT1 & ACT2 & ACT3 & ACT4 & ACT5 & ACT6 & ACT7 & ACT8 & ACT9 & ACT10; ACT12.t = ACT0 & ACT1 & ACT2 & ACT3 & ACT4 & ACT5 & ACT6 & ACT7 & ACT8 & ACT9 & ACT10 & ACT11; ACT13.t = ACT0 & ACT1 & ACT2 & ACT3 & ACT4 & ACT5 & ACT6 & ACT7 & ACT8 & ACT9 & ACT10 & ACT11 & ACT12; [ACT13..0].ckmux = A6; DP = DP_EN & ((!LCLK & ACT13) # (LCLK & !ACT13)); /* * This logical circuit is used to generate a positive pulse that * is one clock duration in length that begins on the next falling * edge after the begining of a write to register location 0x70 * and ends on the next falling edge of the clock. The RTC chip * is tollerant of the CS line rising between accesses to the * virtual register location latch address 0x70 and the register * read/write address 0x71 */ Pinnode = RTC_QO; Pinnode = RTC_QE; RTC_QE.t = !RTC_QE; RTC_QE.ar = !(RTC_ADDR_DEC & IOW); RTC_QE.ckmux = !BCLK; RTC_QO.t = RTC_QE $ !RTC_QO; RTC_QO.ar = !(RTC_ADDR_DEC & IOW); RTC_QO.ckmux = !BCLK; RTC_ALE = RTC_QO; /* RTC select strobes */ Pinnode = RTC_CS_HOLD; RTC_CS_HOLD.t = 'b'0; RTC_CS_HOLD.ckmux = BCLK; RTC_CS_HOLD.ap = RESET # RTC_ADDR_DEC; RTC_CS_HOLD.ar = RTC_DATA_DEC; RTC_CS = RTC_COMBINED # !RTC_CS_HOLD; RTC_OE = RTC_DATA_DEC & IOR; RTC_WE = RTC_DATA_DEC & IOW;