Name jride_main; Assembly 0003; Revision P2 1.0; PartNo U4 ATF1508AS; Device f1508ispplcc84; Company Retrotronics.org; Designer Alan H.; Location None; Date October 2011; property ATMEL { xor_synthesis=on }; property ATMEL { logic_doubling=on }; property ATMEL { jtag=on }; PROPERTY ATMEL { preassign keep }; PROPERTY ATMEL { TMS_pullup=on }; PROPERTY ATMEL { TDI_pullup=on }; /* * Pin assignments * * Make all data and address outputs fast slew and all chip selects slow */ Pin 1 = RESET; Pin 83 = CLK; Pin 74 = A0; Pin 73 = A1; Pin 70 = A2; Pin 69 = A3; Pin 68 = A4; Pin 67 = A5; Pin 64 = A6; Pin 65 = A7; Pin 2 = A8; Pin 84 = A9; Pin 77 = A10; Pin 81 = A11; Pin 63 = A12; Pin 4 = A13; Pin 44 = A14; Pin 60 = A15; Pin 45 = A16; Pin 61 = A17; Pin 46 = A18; Pin 75 = A19; Pin 48 = D0; Pin 49 = D1; Pin 50 = D2; Pin 55 = D3; Pin 54 = D4; Pin 52 = D5; Pin 56 = D6; Pin 57 = D7; Pin 29 = IDE_D0; Pin 24 = IDE_D1; Pin 22 = IDE_D2; Pin 21 = IDE_D3; Pin 17 = IDE_D4; Pin 15 = IDE_D5; Pin 12 = IDE_D6; Pin 11 = IDE_D7; Pin 9 = IDE_D8; Pin 10 = IDE_D9; Pin 16 = IDE_D10; Pin 18 = IDE_D11; Pin 20 = IDE_D12; Pin 25 = IDE_D13; Pin 27 = IDE_D14; Pin 28 = IDE_D15; Pin 36 = IDE_A0; /* also ROM_A15 */ Pin 34 = IDE_A1; /* also ROM_A16 */ Pin 33 = IDE_A2; /* also ROM_A18 */ Pin 30 = !IDE_RD; Pin 31 = !IDE_WR; Pin 79 = !MEMWR; Pin 80 = !MEMRD; Pin 58 = !RAM_CE0; Pin 76 = !RAM_CE1; Pin 41 = !ROM_CE; Pin 5 = !DIP4; Pin 6 = !DIP5; Pin 8 = !DIP6; Pin 35 = !IDE_CE0; Pin 37 = !IDE_CE1; Pin 39 = ROM_A14; Pin 40 = ROM_A17; Pin 51 = PLD_CE; /* * Register field map for internal write only registers * accessed immedaitely after the IDE register window * used to control the ROM disk remap window address, * target page, and upper memory RAM fill-in. * * Select 0 Bit 0 reg0 RAM fill enable 0xC0000 -> 0xC3FFF * 0 1 reg1 RAM fill enable 0xC4000 -> 0xC7FFF * 0 2 reg2 RAM fill enable 0xC8000 -> 0xCBFFF * 0 3 reg3 RAM fill enable 0xCC000 -> 0xCFFFF * 0 4 reg4 RAM fill enable 0xD0000 -> 0xD7FFF * 0 5 reg5 RAM fill enable 0xD8000 -> 0xDFFFF * 0 6 reg6 RAM fill enable 0xE0000 -> 0xE7FFF * 0 7 reg7 RAM fill enable 0xE8000 -> 0xEFFFF * * Select 1 Bit 0 reg8 ROM remap target page bit 0 (A14) * 1 1 reg9 ROM remap target page bit 1 (A15) * 1 2 reg10 ROM remap target page bit 2 (A16) * 1 3 reg11 ROM remap target page bit 3 (A17) * 1 4 reg12 ROM remap target page bit 4 (A18) * 1 5 reg13 ROM remap window A14 reference * 1 6 reg14 ROM remap window A15 reference * 1 7 reg15 ROM remap window enable/disable */ Pinnode = [reg15..0]; REMAP_A18 = reg12; REMAP_A17 = reg11; REMAP_A16 = reg10; REMAP_A15 = reg9; REMAP_A14 = reg8; ROM_A17 = REMAP_WIN & REMAP_A17; ROM_A14 = REMAP_WIN & REMAP_A14; MAP15 = reg14; MAP14 = reg13; MAPE = reg15; RAM_REGION_1 = reg0; RAM_REGION_2 = reg1; RAM_REGION_3 = reg2; RAM_REGION_4 = reg3; RAM_REGION_5 = reg4; RAM_REGION_6 = reg5; RAM_REGION_7 = reg6; RAM_REGION_8 = reg7; /* * Side-car RAM address decoding logic. The lower * 736 KB fill is always on. * * Four 16KB option ROM regions in the C0000 block * can be optionally enabled by the JR-IDE option * ROM BIOS based on which ones it itself is not * assigned to and which one it is not using for * the flash access window - as well as excluding * enabling any that have other ROM BIOS blocks * present. * * Additionally the JR-IDE option ROM BIOS may * enable RAM fill for the traditional cartridge * ROM regions. It then could shadow actual * cartridge ROM images from flash to this RAM * based on a boot menu selection. */ field BLOCK = [A19..0]; RAM_DEC0 = BLOCK:[20000..7FFFF]; RAM_DEC1 = (BLOCK:[80000..B7FFF]) # (BLOCK:[C0000..C3FFF] & RAM_REGION_1) # (BLOCK:[C4000..C7FFF] & RAM_REGION_2) # (BLOCK:[C8000..CBFFF] & RAM_REGION_3) # (BLOCK:[CC000..CFFFF] & RAM_REGION_4) # (BLOCK:[D0000..D7FFF] & RAM_REGION_5) # (BLOCK:[D8000..DFFFF] & RAM_REGION_6) # (BLOCK:[E0000..E7FFF] & RAM_REGION_7) # (BLOCK:[E8000..EFFFF] & RAM_REGION_8); /* * 16KB option ROM decode window at 16KB steps between * C0000 & D0000 matched against DIP switches 4 & 5 */ Pinnode = OPTION_WIN; OPTION_WIN = A19 & A18 & !A17 & !A16 & !(A15 $ DIP4) & !(A14 $ DIP5); /* * Break down of the 16KB option ROM decode window. * 14.5KB of ROM space, a virtualize 512 byte IDE sector * access buffer, 16 IDE device registers, and two * internal registers with-in this space. The 1006 * trailing addresses are filled in with scratch RAM * for JR-IDE option ROM BIOS use. */ field SUBADDR = [A13..0]; ROM_AREA = OPTION_WIN & SUBADDR:[0000..39FF]; IDE_DATA = OPTION_WIN & SUBADDR:[3A00..3BFF]; IDE_WIN = OPTION_WIN & SUBADDR:[3C00..3C0F]; REG_CS0 = OPTION_WIN & SUBADDR:[3C10..3C10]; REG_CS1 = OPTION_WIN & SUBADDR:[3C11..3C11]; SUB_RAM = OPTION_WIN & SUBADDR:[3C12..3FFF]; NP_IDE_DATA = SUBADDR:[3A00..3BFF]; /* * Enable RAM chip selects for main memory, upper memory * blocks, and option ROM scratch RAM areas */ RAM_CE0 = RAM_DEC0 & (MEMRD # MEMWR); RAM_CE1 = (SUB_RAM # RAM_DEC1) & (MEMRD # MEMWR); /* * 16KB flash disk remap window positioned at 16KB steps * between C0000 & D0000 matched against address in remap * register and remap enable control (bit 0) */ Pinnode = REMAP_WIN; REMAP_WIN = A19 & A18 & !A17 & !A16 & !(A15 $ MAP15) & !(A14 $ MAP14) & MAPE; /* Flash/ROM chip select output signal */ ROM_CE = (MEMRD # MEMWR) & ((ROM_AREA & DIP6) # REMAP_WIN); /* * Three ROM address lines are multiplexed with the * IDE address lines. For remap window access, they * carry the remap register values. For the IDE * sector window, they zero to IDE address 0 (data * register), and for all other IDE access they * pass through from A2..0. */ IDE_A0 = (REMAP_WIN & REMAP_A15) # (IDE_WIN & A0); IDE_A1 = (REMAP_WIN & REMAP_A16) # (IDE_WIN & A1); IDE_A2 = (REMAP_WIN & REMAP_A18) # (IDE_WIN & A2); /* The strobes are simply buffered through */ IDE_RD = MEMRD; IDE_WR = MEMWR; /* * IDE strobe selection logic. These should be left * at slow slew while data and address lines fast to * (hopefully) prevent gate racing. I haven't yet * computed all the propagation times (by hand - FU Atmel) */ IDE_DATA_SEL = NP_IDE_DATA & ((!A0 & MEMRD) # (A0 & MEMWR)); IDE_CE0 = OPTION_WIN & (SUBADDR:[3C00..3C07] # IDE_DATA_SEL); IDE_CE1 = OPTION_WIN & SUBADDR:[3C08..3C0F]; /* * Provide some combinatorial logic for pre-decoding * addresses for the secondary PLD that handles RTC * and POST. It will further qualify these address * ranges internally as well as against the IO R/W * strobes. */ PLD_CE = ([A15..0]:[10..13] # [A15..0]:[70..73]); /* Internal register loads */ reg15.d = D7; reg14.d = D6; reg13.d = D5; reg12.d = D4; reg11.d = D3; reg10.d = D2; reg9.d = D1; reg8.d = D0; [reg15..8].ar = RESET; [reg15..8].ck = MEMWR & REG_CS1 & CLK; reg7.d = D7; reg6.d = D6; reg5.d = D5; reg4.d = D4; reg3.d = D3; reg2.d = D2; reg1.d = D1; reg0.d = D0; [reg7..0].ar = RESET; [reg7..0].ck = MEMWR & REG_CS0 & CLK; /* * Bus steering and latch logic for 16-bit IDE data window * reads and writes. A single 8-bit latch is used to for * both directions. You could use two latches here, one * for read and one for write, but so far synthesis has * shown no combinatorial logic savings. * A rep movsw is used to transfer a sector. The 8088/V20 * will break each 16-bit mov into two successive 8-bit * bus cycles. When transfering a sector in from the drive, * the CS is asserted on the even address location and the * upper IDE byte is caught by the latch and returned during * the odd cycle. When transfering a sector out to the drive, * the CS is asserted on the odd address location presenting * the IDE lower byte latched in during the even cycle and * the IDE upper byte from the odd cycle ISA bus value. * * The switch power savings that could be gained by limiting * latching to only the IDE sector window is not worth the * combinatorial logic expense. */ Pinnode = [DR7..0]; DR7.d = IDE_D15; DR6.d = IDE_D14; DR5.d = IDE_D13; DR4.d = IDE_D12; DR3.d = IDE_D11; DR2.d = IDE_D10; DR1.d = IDE_D9; DR0.d = IDE_D8; [DR7..0].ar = RESET; [DR7..0].ck = !MEMRD # !IDE_DATA # A0; Pinnode = [DW7..0]; DW7.d = D7; DW6.d = D6; DW5.d = D5; DW4.d = D4; DW3.d = D3; DW2.d = D2; DW1.d = D1; DW0.d = D0; [DW7..0].ar = RESET; [DW7..0].ck = MEMWR & IDE_DATA & !A0 & CLK; /* * 16-bit steering logic is only ever invoked for the * virtual IDE sector window selected below. In such * cases, the ISA bus will be presenting the upper byte * and the lower byte will come from the latch value * loaded during the previous even address write cycle. * * For normal 8-bit writes, the lower byte of the * buffered bus is a straight pass-through of the ISA * bus data lines. */ IDE_D15 = D7; IDE_D14 = D6; IDE_D13 = D5; IDE_D12 = D4; IDE_D11 = D3; IDE_D10 = D2; IDE_D9 = D1; IDE_D8 = D0; IDE_D7 = (A9 & DW7) # (!A9 & D7); IDE_D6 = (A9 & DW6) # (!A9 & D6); IDE_D5 = (A9 & DW5) # (!A9 & D5); IDE_D4 = (A9 & DW4) # (!A9 & D4); IDE_D3 = (A9 & DW3) # (!A9 & D3); IDE_D2 = (A9 & DW2) # (!A9 & D2); IDE_D1 = (A9 & DW1) # (!A9 & D1); IDE_D0 = (A9 & DW0) # (!A9 & D0); [IDE_D15..0].oe = MEMWR; /* * The only thing on the buffered data bus is the IDE * connector. Enable output on reads for both IDE * access windows (sector & register). * * Bus steering is based on: * * - Sector window even read: IDE lower -> ISA (latches upper) * - Sector window odd read: Latched IDE upper -> ISA * - Register access window: IDE lower -> ISA (pass-through) */ READ_LATCH = A9 & A0; D0 = (READ_LATCH & DR0) # (!READ_LATCH & IDE_D0); D1 = (READ_LATCH & DR1) # (!READ_LATCH & IDE_D1); D2 = (READ_LATCH & DR2) # (!READ_LATCH & IDE_D2); D3 = (READ_LATCH & DR3) # (!READ_LATCH & IDE_D3); D4 = (READ_LATCH & DR4) # (!READ_LATCH & IDE_D4); D5 = (READ_LATCH & DR5) # (!READ_LATCH & IDE_D5); D6 = (READ_LATCH & DR6) # (!READ_LATCH & IDE_D6); D7 = (READ_LATCH & DR7) # (!READ_LATCH & IDE_D7); [D7..0].oe = MEMRD & OPTION_WIN & SUBADDR:[3A00..3C0F];