module pfname ( 
	input rst,
	input [3:0] sys_sw,
	output [3:0] sys_led,

	input uart_rx,
	output uart_tx,

	// 64MB SDR SDRAM

	output [12:0]   dram_A,       // DRAM address bus (x13)
	inout  [15:0]   dram_DQ,      // DRAM data bus (x16)
	output [1:0]    dram_BA,      // DRAM bank address (x2)
	output [1:0]    dram_DQMn,    // DRAM write data mask (x2)
	output          dram_RASn,    // DRAM row address strobe
	output          dram_CASn,    // DRAM column address strobe
	output          dram_CSn,     // DRAM chip select
	output          dram_WEn,     // DRAM write enable
	output          dram_CLK,     // DRAM clock
	output          dram_CKE      // DRAM clock enable
);

	// On-Chip Oscillator -> System Clock
	wire clk; 

	defparam OSCH_inst.NOM_FREQ = "24.18"; 
	OSCH OSCH_inst (.OSC(clk), .SEDSTDBY(), .STDBY(1'b0)); 

     // Reset Generator
	wire sys_rst;

	reset_gen reset_gen_inst
	(
		.clk(clk),
		.rst_in(rst),
		.rst_out(sys_rst)
	);

	// Wishbone M->S
	wire        wb_clk;
	wire        wb_rst;
	wire [31:0] wb_adr;
	wire  [7:0] wb_dat_ms;
	wire        wb_we;
	wire        wb_stb;
	wire        wb_cyc;
	wire        wb_lck;
	wire  [2:0] wb_cti;
	wire  [1:0] wb_bte;
	wire        wb_sel;

	// Wishbone S->M
	wire  [7:0] wb_dat_sm;
	wire        wb_ack;
	wire        wb_rty;
	wire        wb_err;

	assign wb_clk = clk;
	assign wb_rst = sys_rst;


	wire [7:0] irqs;

	wire [7:0] sdram_dat;
	wire sdram_ack;
	wire sdram_err;
	wire sdram_rty;
	wire sdram_cs;

	wire [7:0] uart_dat;
	wire uart_ack;
	wire uart_err;
	wire uart_rty;
	wire uart_cs;
	wire uart_irq;


	assign wb_dat_sm = sdram_cs ? sdram_dat : uart_cs ? uart_dat : 8'b00000000;
	assign wb_err = wb_cyc & !((sdram_cs & !sdram_err) | (uart_cs & !uart_err));
	assign wb_ack = sdram_cs ? sdram_ack : uart_cs ? uart_ack : 0;
	assign wb_rty = sdram_cs ? sdram_rty : uart_cs ? uart_rty : 0;

	assign uart_cs = (wb_adr[31:4] == 28'b10000000_00000000_00000000_0000);
	assign sdram_cs = (wb_adr[31:24] == 28'b00000001);


	lm8 #(

		.CFG_REGISTER_16(1),
		.CFG_REGISTER_32(0),
		.CFG_CALL_STACK_8(0),
		.CFG_CALL_STACK_16(1),
		.CFG_CALL_STACK_32(0),
		.CFG_PROM_SIZE(1024),
		.CFG_PROM_INIT_FILE("../lm8_src/bin/test_code.mem"),
		.CFG_PROM_INIT_FILE_FORMAT("hex"),

		.SP_BASE_ADDRESS(32'h0),
		.SP_SIZE(1024),
		.CFG_SP_INIT_FILE("../lm8_src/bin/test_data.mem"),
		.CFG_SP_INIT_FILE_FORMAT("hex"),

		.CFG_EXT_SIZE_8(0),
		.CFG_EXT_SIZE_16(1),
		.CFG_EXT_SIZE_32(0),

		.LATTICE_FAMILY("MachXO2")

	) lm8_inst ( 

		.D_ADR_O (wb_adr),
		.D_DAT_O (wb_dat_ms),
		.D_DAT_I (wb_dat_sm),
		.D_SEL_O (wb_sel),
		.D_WE_O  (wb_we),
		.D_ACK_I (wb_ack),
		.D_ERR_I (wb_err),
		.D_RTY_I (wb_rty),
		.D_CTI_O (wb_cti),
		.D_BTE_O (wb_bte),
		.D_LOCK_O(wb_lck),
		.D_CYC_O (wb_cyc),
		.D_STB_O (wb_stb),

		.interrupts(irqs),
		.clk_i (wb_clk),
		.rst_i (wb_rst)
	);


	sdram #(

		.SDRAM_WB_DAT_WIDTH(8),
		.SDRAM_WB_ADR_WIDTH(4),
		.OUTPUT_PORTS_ONLY(0),
		.INPUT_PORTS_ONLY(0),
		.TRISTATE_PORTS(0),
		.BOTH_INPUT_AND_OUTPUT(1),
		.DATA_WIDTH(4),
		.INPUT_WIDTH(4),
		.OUTPUT_WIDTH(4),
		.IRQ_MODE(1),
		.LEVEL(1),
		.EDGE(0),
		.EITHER_EDGE_IRQ(0),
		.POSE_EDGE_IRQ(1),
		.NEGE_EDGE_IRQ(0)

	) sdram_inst (

		.SDRAM_ADR_I(wb_adr[3:0]),
		.SDRAM_DAT_I(wb_dat_ms),
		.SDRAM_DAT_O(sdram_dat),
		.SDRAM_SEL_I(wb_sel),
		.SDRAM_WE_I(wb_we),
		.SDRAM_ACK_O(sdram_ack),
		.SDRAM_ERR_O(sdram_err),
		.SDRAM_RTY_O(sdram_rty),
		.SDRAM_CTI_I(wb_cti),
		.SDRAM_BTE_I(wb_bte),
		.SDRAM_LOCK_I(wb_lck),
		.SDRAM_CYC_I(wb_cyc & sdram_cs),
		.SDRAM_STB_I(wb_stb & sdram_cs),
		.PIO_IN(),
		.PIO_BOTH_IN(sys_sw),
		.PIO_OUT(),
		.PIO_BOTH_OUT(sys_led),
		.PIO_IO(),
		.IRQ_O(sdram_irq),
		.CLK_I(wb_clk),
		.RST_I(wb_rst)
	);


	uart_core #(

		.UART_WB_DAT_WIDTH(8),
		.UART_WB_ADR_WIDTH(4),
		.CLK_IN_MHZ(24),
		.BAUD_RATE(115200),
		.STDOUT_SIM(0),
		.STDOUT_SIMFAST(0),
		.LCR_DATA_BITS(8),
		.LCR_STOP_BITS(1),
		.LCR_PARITY_ENABLE(0),
		.LCR_PARITY_ODD(0),
		.LCR_PARITY_STICK(0),
		.LCR_SET_BREAK(0),
		.FIFO(0)

	) uart_inst (

		.UART_ADR_I(wb_adr[3:0]),
		.UART_DAT_I(wb_dat_ms),
		.UART_DAT_O(uart_dat),
		.UART_SEL_I(wb_sel),
		.UART_WE_I(wb_we),
		.UART_ACK_O(uart_ack),
		.UART_ERR_O(uart_err),
		.UART_RTY_O(uart_rty),
		.UART_CTI_I(wb_cti),
		.UART_BTE_I(wb_bte),
		.UART_LOCK_I(wb_lck),
		.UART_CYC_I(wb_cyc & uart_cs),
		.UART_STB_I(wb_stb & uart_cs),
		.SIN(uart_rx),
		.SOUT(uart_tx),
		.INTR(uart_irq),
		.CLK(wb_clk),
		.RESET(wb_rst)
	);


	assign irqs[0] = uart_irq;
	assign irqs[1] = 0;
	assign irqs[2] = 0;
	assign irqs[3] = 0;
	assign irqs[4] = 0;
	assign irqs[5] = 0;
	assign irqs[6] = 0;
	assign irqs[7] = 0;

endmodule