module reset_gen (
	input  clk,
	input  rst_in,
	output reg rst_out
);

	localparam COUNT_BITS = 4;
	localparam MAX_COUNT  = (2 **  COUNT_BITS) - 1;
	localparam RST_VAL    =  2 ** (COUNT_BITS  - 1);

	reg [COUNT_BITS-1:0] reset_counter;

	always @(posedge clk or posedge rst_in)
	begin
		if (rst_in)
		begin
			reset_counter <= 0;
		end
		else
		begin
			if (reset_counter < MAX_COUNT)
				reset_counter <= reset_counter + 1;
		end
	end

	always @(posedge clk or posedge rst_in)
	begin
		if (rst_in)
		begin
			rst_out <= 1'b1;
		end
		else
		begin
			if (reset_counter < RST_VAL)
				rst_out <= 1'b1;
			else
				rst_out <= 1'b0;
		end
	end

endmodule