`include "system_conf.v"

module isa_wb_master
(
	// ISA pads

	inout       [7:0] isa_D,        // Data bus (x16)
	input      [19:0] isa_SA,       // System address bus (x20)
	output            isa_IOCHRDY,  // I/O channel ready
	input             isa_SMEMW,    // System memory write strobe
	input             isa_SMEMR,    // System memory read strobe
	input             isa_IOW,      // I/O write strobe
	input             isa_IOR,      // I/O read strobe
	input             isa_AEN,      // DMA address enable

	input             isa_CS,       // Overall card select
 
	input             wb_clk_i,     // Synchronous bus clock
	input             wb_rst_i,     // Asynchronous bus reset

	input       [7:0] wb_dat_i,     // Input data
	output reg  [7:0] wb_dat_o,     // Output data
	output reg [31:0] wb_adr_o,     // Address
	output reg        wb_we_o,      // Cycle direction
	output reg        wb_tga_o,     // Address tag: 1 = I/O, 0 = MEM
	output reg        wb_stb_o,     // Cycle strobe
	output reg        wb_cyc_o,     // Bus busy
	input             wb_ack_i      // Slave completion ack
);

	/*
	 * ISA -> WB strobe propagation
	 */

	wire io_cycle;
	wire mem_cycle;
	wire write_cycle;

	assign    io_cycle =  (isa_IOW | isa_IOR) & !isa_AEN;
	assign   mem_cycle = isa_SMEMW | isa_SMEMR;
	assign write_cycle = isa_SMEMW | isa_IOW;

	/*
	 * ISA -> WB propagation
	 *
	 * We're crossing a time domain here.  Ideally the
	 * outgoing wishbone signals should be registered
	 * here per the spec to prevent transients on the
	 * ISA bus from generating false state transitions
	 * on the WB bus.  For now these are registered on
	 * the rising edge to give a minimum of one full WB
	 * for slave logic to settle.  It conserves a little
	 * switching power as a bonus by not having the
	 * internal address logic in a free running cascade.
	 *
	 * In the future some experiemntation/analysis should
	 * be done to register on a negative edge or not at
	 * all to decrease latency.
	 */

	always @(posedge wb_clk_i)
	begin

		wb_adr_o[19:0]  <= isa_SA;
		wb_adr_o[31:20] <= 0;

		wb_dat_o <= isa_D;

		wb_cyc_o <= io_cycle | mem_cycle;
		wb_stb_o <= io_cycle | mem_cycle;
		wb_we_o  <= write_cycle;
		wb_tga_o <= io_cycle;

	end

	/*
	 * WB -> ISA propagation and ready signaling
	 *
	 * Again we're crossing a time domain.  However
	 * we must hold the data until the command strobes
	 * drop on the ISA bus (and the master has read it).
	 *
	 * During address decode, if we determine the card
	 * has been selected, we need to stretch the ready
	 * signal until the data is being drive on the ISA
	 * bus
	 */

	assign isa_D = (!write_cycle && wb_ack_i) ? wb_dat_i : 8'hzz;
	assign isa_IOCHRDY = !(isa_CS && !wb_ack_i);

endmodule