Starting process: Module

Starting process: 

SCUBA, Version Diamond_3.0_Production (94)
Thu Jan 23 15:32:17 2014

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.

BEGIN SCUBA Module Synthesis

    Issued command   : C:\lscc\diamond\3.0\ispfpga\bin\nt\scuba.exe -w -n pll0 -lang verilog -synth synplify -arch xo2c00 -type pll -fin 26 -fclkop 39 -fclkop_tol 0.0 -fclkos 39 -fclkos_tol 0.0 -fclkos2 14.7 -fclkos2_tol 10.0 -fclkos3 20 -fclkos3_tol 0.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 90 -trims_r -phases2 0 -phases3 0 -phase_cntl STATIC -fb_mode 1 -lock -e 
    Circuit name     : pll0
    Module type      : pll
    Module Version   : 5.4
    Ports            : 
	Inputs       : CLKI
	Outputs      : CLKOP, CLKOS, CLKOS2, CLKOS3, LOCK
    I/O buffer       : not inserted
    EDIF output      : suppressed
    Verilog output   : pll0.v
    Verilog template : pll0_tmpl.v
    Verilog purpose  : for synthesis and simulation
    Bus notation     : big endian
    Report output    : pll0.srp
    Estimated Resource Usage:

END   SCUBA Module Synthesis

File: pll0.lpc created.


End process: completed successfully.


Total Warnings:  0

Total Errors:  0