`include "system_conf.v"

module arbiter2
(
	// Master Port0
	input  [31:0] WBM0_ADR_O,
	input   [7:0] WBM0_DAT_O,
	output  [7:0] WBM0_DAT_I,
	input         WBM0_SEL_O,
	input         WBM0_WE_O,
	output        WBM0_ACK_I,
	output        WBM0_ERR_I,
	output        WBM0_RTY_I,
	input   [2:0] WBM0_CTI_O,
	input   [1:0] WBM0_BTE_O,
	input         WBM0_LOCK_O,
	input         WBM0_CYC_O,
	input         WBM0_STB_O,

	// Master Port1
	input  [31:0] WBM1_ADR_O,
	input   [7:0] WBM1_DAT_O,
	output  [7:0] WBM1_DAT_I,
	input         WBM1_SEL_O,
	input         WBM1_WE_O,
	output        WBM1_ACK_I,
	output        WBM1_ERR_I,
	output        WBM1_RTY_I,
	input   [2:0] WBM1_CTI_O,
	input   [1:0] WBM1_BTE_O,
	input         WBM1_LOCK_O,
	input         WBM1_CYC_O,
	input         WBM1_STB_O,

	// Slave Port
	output [31:0] WBS_ADR_I,
	output  [7:0 ]WBS_DAT_I,
	input   [7:0 ]WBS_DAT_O,
	output        WBS_SEL_I,
	output        WBS_WE_I,
	input         WBS_ACK_O,
	input         WBS_ERR_O,
	input         WBS_RTY_O,
	output  [2:0] WBS_CTI_I,
	output  [1:0] WBS_BTE_I,
	output        WBS_LOCK_I,
	output        WBS_CYC_I,
	output        WBS_STB_I,

	input clk,
	input reset
);




	reg [1:0] selected;
	reg locked;


	always @(posedge clk or posedge reset)
	begin
		if (reset) begin
			selected <= #1 0;
			locked   <= #1 0;
		end
		else begin
			if (selected == 0) begin
				if (WBM0_STB_O) begin
					selected <= #1 2'd1;
					locked   <= #1 WBM0_LOCK_O;
				end
				else if (WBM1_STB_O) begin
					selected <= #1 2'd2;
					locked   <= #1 WBM1_LOCK_O;
				end
			end
			else if (selected == 2'd1) begin
				if ((WBS_ACK_O || WBS_ERR_O || locked) && ((WBM0_CTI_O == 3'b000) || (WBM0_CTI_O == 3'b111) || locked) && !WBM0_LOCK_O) begin
					selected <= #1 0;
					locked <= #1 0;
				end
			end
			else if (selected == 2'd2) begin
				if ((WBS_ACK_O || WBS_ERR_O || locked) && ((WBM1_CTI_O == 3'b000) || (WBM1_CTI_O == 3'b111) || locked) && !WBM1_LOCK_O) begin
					selected <= #1 0;
					locked <= #1 0;
				end
			end
		end
	end

	assign WBS_ADR_I =
		(selected == 2'd1 ? WBM0_ADR_O : 
		(selected == 2'd2 ? WBM1_ADR_O : 0));
	assign WBS_DAT_I = 
		(selected == 2'd1 ? WBM0_DAT_O : 
		(selected == 2'd2 ? WBM1_DAT_O : 0));
	assign WBS_SEL_I = 
		(selected == 2'd1 ? WBM0_SEL_O : 
		(selected == 2'd2 ? WBM1_SEL_O : 0));
	assign WBS_WE_I = 
		(selected == 2'd1 ? WBM0_WE_O : 
		(selected == 2'd2 ? WBM1_WE_O : 0));
	assign WBS_CTI_I = 
		(selected == 2'd1 ? WBM0_CTI_O : 
		(selected == 2'd2 ? WBM1_CTI_O :  0));
	assign WBS_BTE_I = 
		(selected == 2'd1 ? WBM0_BTE_O : 
		(selected == 2'd2 ? WBM1_BTE_O :  0));
	assign WBS_LOCK_I = 
		(selected == 2'd1 ? WBM0_LOCK_O : 
		(selected == 2'd2 ? WBM1_LOCK_O :  0));
	assign WBS_CYC_I = 
		(selected == 2'd1 ? WBM0_CYC_O : 
		(selected == 2'd2 ? WBM1_CYC_O :  0));
	assign WBS_STB_I = 
		(selected == 2'd1 ? WBM0_STB_O : 
		(selected == 2'd2 ? WBM1_STB_O :  0));

	assign WBM0_DAT_I = WBS_DAT_O;
	assign WBM0_ACK_I = (selected == 2'd1 ? WBS_ACK_O : 0);
	assign WBM0_ERR_I = (selected == 2'd1 ? WBS_ERR_O : 0);
	assign WBM0_RTY_I = (selected == 2'd1 ? WBS_RTY_O : 0);

	assign WBM1_DAT_I = WBS_DAT_O;
	assign WBM1_ACK_I = (selected == 2'd2 ? WBS_ACK_O : 0);
	assign WBM1_ERR_I = (selected == 2'd2 ? WBS_ERR_O : 0);
	assign WBM1_RTY_I = (selected == 2'd2 ? WBS_RTY_O : 0);

endmodule